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Fabrication

Fabrication processes include epitaxy, etching, ion-implantation, and deposition. Modeling and simulation contribute to improved understanding and optimization of deposition and post-deposition procedures. For example, the deposition of a possible high-k dielectric material on Si by Atomic Layer Deposition via particular reaction sequences have been elucidated leading to improved reaction and process control (reference 1). For example, Figure 1 shows an atomistic model for the Si/SiOx/HfO2 interface resulting from the ‘heal defect’ strategy (reference 2) and atomic layer deposition modeling (reference 3).

Related Software and Services:

Accelrys provides a wide range of solutions for fabrication- related issues.

  • Materials Studio DMol3 - density functional theory (DFT) quantum mechanical code to simulate chemical processes and predict properties
  • Materials Studio CASTEP - density functional theory (DFT) quantum mechanical code to simulate the properties of solids, interfaces, and surfaces
  • Materials Studio GULP - range of materials forcefields for predicting structural, electronic, and materials properties and for modeling dynamic processes
  • Contract Research & Scientific Consulting Services - organizations who are either resource-restricted or feel that they have no computational chemistry expertise choose Accelrys’ Contract Research Services to help find solution for their business-critical scientific needs

Bibliography: Fabrication

  1. “Theoretical study of reaction mechanisms of ZrCl4 with hydrated and hydroxylated Si(100) surfaces,” M. Petersen, Comp. Mat. Sci. 30, 77 (2004).
    2.
  2. “Theoretical study of reaction mechanisms of ZrCl4 with hydrated and hydroxylated Si(100) surfaces,” M. Petersen, Comp. Mat. Sci. 30, 77 (2004).1. “Modeling HfO2/SiO2/Si interface”, J. L. Gavartin, A. L. Shluger, Microelectronic Engineering 84 (2007) 2412–2415.
  3. J.L. Gavartin, L. Fonseca, G.I. Bersuker, and A.L. Shluger. Ab initio modeling of structure and defects at the HfO2/Si interface. Microelectronics Engineering 80C, 412-415 (2005).