Materials Development for CMOS and Memory Devices

Accelrys technology is applicable in multiple domains of research in the electronics industry, for example in silicon and CMOS technology, where researchers are challenged with taking silicon and CMOS technology to its limits, and finding longer terms solutions beyond silicon.

Gate Oxides

A traditional transistor with a structure consists of all silicon materials, with a doped Si semiconductor, a silicon-oxide dielectric layer, and a polycrystalline silicon (metallic) gate (Figure 1). However, as feature size, gate length and dielectric layer thickness have decreased, and power has increased, new materials need to be used for both high and low power applications (Figure 2). For example, transistor gate leakage associated with the ever-thinning gate dielectric made of SiO2 has been recognized by the industry as one of the most formidable technical challenges facing Moore's Law in this decade. A solution used, for example by Intel, is to move to alternate materials that are thicker to address leakage, yet at the same time preserve the high capacitance that is desirable for good transistor performance. This class of materials has a property known by the moniker "high-k." (Figure 3). Accelrys' Materials Studio DMol³ and CASTEP software provide solutions that make it possible to predict the structural and electronic properties interfaces, including atomic disorder. Calculated band alignment allows for instructive analysis of band gap variation, dipole formation and defects for example (see references 1 and 2).

 Related Software and Services

• Materials Studio DMol³ - density functional theory (DFT) quantum mechanical code to simulate chemical processes and predict properties
• Materials Studio CASTEP - density functional theory (DFT) quantum mechanical code to simulate the properties of solids, interfaces, and surfaces
• Contract Research & Scientific Consulting Services - organizations who are either resource-restricted or feel that they have no computational chemistry expertise choose Accelrys’ Contract Research Services to help find solution for their business-critical scientific needs

Interconnects

In contrast to the gate oxides, interconnects require low resistivity [low-k] materials such as copper; but, such metals can oxidize or diffuse, poisoning the device. The development of new low dielectric constant (low k) materials become increasingly important for microelectronics as interconnect delays limit circuit performance. Accelrys Materials' Studio DMol³ and CASTEP software, in combination with Accelrys’ customer-goal-oriented Contract Research Services, provide solutions for elucidating the structure of new complex materials. For example, these solutions can help chemists analyze and assign Fourier-transform infrared spectra, build realistic atomistic models, and calculate mechanical and electronic properties of low k dielectrics (see ref 1). Similarly, Accelrys solutions enable the prediction of structural and electronic properties of interfaces, including atomic disorder of new gate oxide materials. Calculated band alignment allows for instructive analysis of band gap variation, dipole formation and defects for example (see references 2 and 3).

 Related Software and Services

• Materials Studio DMol³ - density functional theory (DFT) quantum mechanical code to simulate chemical processes and predict properties
• Materials Studio CASTEP - density functional theory (DFT) quantum mechanical code to simulate the properties of solids, interfaces, and surfaces
• Contract Research & Scientific Consulting Services - organizations who are either resource-restricted or feel that they have no computational chemistry expertise choose Accelrys’ Contract Research Services to help find solution for their business-critical scientific needs

Bibliography: Materials Development for CMOS and Memory Devices

1. “Density functional theory analysis of infrared modes in carbon-incorporated SiO2”, M. Petersen, M. T. Schulberg and L. A. Gochberg, Applied Physics Letters 82 No. 13 (2003) pp.2041-2043
2. “Thermodynamic stability and band alignment at a metal-high-k dielectric interface”, A. Demkov, Physical Review B 74 (2006) 085310.
3. “Modeling HfO2/SiO2/Si interface”, J. L. Gavartin, A. L. Shluger, Microelectronic Engineering 84 (2007) 2412–2415.